Cadence introduces first Low Power Kit

Bangalore, May 17: Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced the industry's first Low Power Kit enabling engineers to adopt low power techniques regardless of previous experience, with reduced risk, cost and development time.

The Cadence® Low Power Methodology Kit brings together a comprehensive low power methodology, best practices and flows, all demonstrated and proven on a representative design including leading first and third party IP and Cadence applicability consulting services.

This Cadence Kit enables chip designers to implement low power techniques and to accelerate technology-specific product development critical for today's electronics in market segments ranging from handheld wireless devices to mainframes. With this Kit, designers are able to achieve shorter, more predictable design cycles using reusable flows; covering logic design, verification and implementation. The Common Power Format (CPF), an Si2 format for specifying power-saving techniques, is used to ensure consistency throughout the flows.

This Kit is highly modularized, providing not only a holistic methodology, but allowing for incremental adoption. These modules are combined to create six new flows utilizing existing tools: Low Power Functional Simulation, RTL Synthesis, Design for Test and ATPG, Place and Route, Formal Implementation Verification and Power Grid Signoff. Additional modules provide detailed tradeoff analysis, planning, and infrastructure.

Cadence Kits enable IC designers to accelerate technology-specific product development and address design challenges in EDA technology segments such as Analog Mixed Signal, Silicon-in-Package (SiP), coverage-driven functional verification, and Radio Frequency Integrated Circuit (RFIC) applications by combining verified methodologies and flows, demonstrated on a segment-representative design and packaged with Applicability Consulting. By using Cadence Kits, customers can focus more of their design resources on design differentiation rather than developing design infrastructure.

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