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Synopsys delivers first complete SystemVerilog Design

Written by: Staff

Bangalore, Mar 21: Synopsys, a world leader in semiconductor design software, today (Mar 21, 2006) announced that it now supported the SystemVerilog language throughout its suite of design and verification products, extending its SystemVerilog leadership and registering another industry-first achievement.

Important elements in Synopsys' comprehensive SystemVerilog design and verification flow were now made available as the company introduced SystemVerilog verification IP support for its VCS Verification Library, a company release here said.

More than 150 companies were using Synopsys' SystemVerilog solutions to design and verify the advanced systems-on-chips that were used in cutting-edge consumer electronics, networking and telecommunications equipment and computer systems.

Design engineers would leverage on SystemVerilog to express their highly-complex designs more succinctly and accurately, capture critical design attributes with assertions and develop advanced coverage-driven, constrained-random testbenches, the release said.


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